1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a plurality of types of transistors are formed within one chip and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
As a semiconductor device in which a plurality of types of transistors (e.g., transistors having different required specifications from each other) are formed within one chip, the following four conventional examples will be described.
First, as a first conventional example, a structure of a DRAM 600 in which a plurality of types of transistors are formed and a method of manufacturing the same will be described. The structure of the DRAM 600 (i.e., cell structure) is shown in FIG. 66.
The DRAM 600 includes not only a memory cell array portion 601 for storing data, but also a peripheral circuit portion (i.e., an address buffer 602, an X decoder 603, a Y decoder 604, a row/column clock portion 605, an I/O pass portion 606, a refresh portion 607), a sense amplifier portion 608, etc.
Although any these portions are formed by transistors, characteristics required for these portions are different from each other. For instance, the memory cell array portion 601 only allows a low leak current, in order to prevent disappearance of data because of a leak current. Meanwhile, a high amount of current is demanded in the peripheral circuit portion so as to enable operations at a high speed. Further, to distinguish a high level from a low level, the sense amplifier portion 608 must operate at a voltage which is half that of the high level, for example. To this end, a transistor which is used for the sense amplifier portion 608 must operate at a low voltage. In short, a plurality of types of transistors which have different characteristics from each other are needed within the DRAM which is formed as one chip.
Comparing threshold values, for instance, a threshold value for a transistor of the memory cell array portion is about 1V and a threshold value for transistors of the peripheral circuit portions are about 0.8V, while a threshold value for the transistor of the sense amplifier portion must be suppressed as low as 0.4V.
A conventional approach for forming these transistors which have different characteristics from each other within one chip is to change an impurity profile of a channel dope layer in accordance with a transistor. In the following, an example where an impurity concentration of a channel dope is changed in accordance with a transistor will be described.
FIG. 67 shows (in a partial view) an example of a structure of a DRAM which is fabricated by a conventional manufacturing method. Cross sections of N-channel MOS transistors T1 to T3 which are used for the sense amplifier portion, the peripheral circuit portion, and the memory cell array portion are shown.
In FIG. 67, the N-channel MOS transistors T1 to T3 are formed within a P-type well layer 101 which is formed on the same semiconductor substrate 1 (of the P-type). The well layer 101 is element-separated by a channel cut layer 102 and a LOCOS layer 2 in such a manner that the N-channel MOS transistors Ti to T3 are formed in regions which are created by element separation.
The N-channel MOS transistor T1 of the sense amplifier portion comprises a pair of source/drain layers 106 formed within the well layer 101 independently of each other but parallel to each other and a pair of low dope drain layers (hereinafter xe2x80x9cLDD layersxe2x80x9d) 107 formed adjacent ts edge portions facing each other of the source/drain layers 106.
The gate oxide film 3 is formed on the LDD layers 107, and a gate electrode 4 is formed on the gate oxide film 3. A side wall oxide film 5 is formed on a side surface of the gate oxide film 3 and the gate electrode 4. Within the well layer 101 under the gate electrode 4, a channel dope layer 103 is formed.
The N-channel MOS transistor T2 of the peripheral circuit portion comprises a pair of source/drain layers 106 formed within the well layer 101 independently of each other but parallel to each other and a pair of LDD layers 107.
The gate oxide film 3 is formed on the LDD layers 107, and a gate electrode 4 is formed on the gate oxide film 3. The side wall oxide film 5 is formed on a side surface of the gate oxide film 3 and the gate electrode 4. Within the well layer 101 under the gate electrode 4, a channel dope layer 104 is formed.
The N-channel MOS transistor T3 of the memory cell array portion comprises a pair of source/drain layers 106 formed within the well layer 101 independently of each other but parallel to each other and a pair of LDD layers 107.
A gate oxide film 3 is formed on the source/drain layers 106 and the LDD layers 107, and a gate electrode 4 is formed on the gate oxide film 3. The side wall oxide film 5 is formed on a side surface of the gate oxide film 3 and the gate electrode 4. Within the well layer 101 under the gate electrode 4, a channel dope layer 105 is formed. The memory cell array portion has a gate array structure in which adjacent gates share one source/drain layer 106. Such structures are arranged successively.
Table 1 shows figures regarding the structures of the N-channel MOS transistors T1 to T3.
In Table 1, impurity dose for forming the channel dope layers of the N-channel MOS transistors T1, T2 and T3 are 1xc3x971012/cm2, 3xc3x971012/cm2 and 5xc3x97102/cm2, respectively. Boron (B) is implanted as an impurity for either layers with the implantation energy of 50 keV.
FIG. 68 shows impurity profiles of the N-channel MOS transistors T1, T7 and T3 forming the sense amplifier portion, the peripheral circuit portion and the memory cell array portion, all of which are shown in FIG. 67, taken at cross sectional portions along A-Axe2x80x2 line, B-Bxe2x80x2 line and C-Cxe2x80x2 line, respectively.
In FIG. 68, a position (i.e., depth) in a cross sectional direction is shown along a horizontal axis and an impurity concentration is shown along a vertical axis. There are the gate electrode (polysilicon layer), the gate oxide film (SiO2 layer) and the well layer (bulk silicon layer) in this order along the horizontal axis from the left-hand side.
As shown in Table 1, the impurity concentration in the gate electrode stays uniformly at the same quantity among any transistors, and therefore, the A-Axe2x80x2 line, the B-Bxe2x80x2 line and the C-Cxe2x80x2 line are one atop the other and shown as overlapping straight lsnes. On the other hand, in the well layer, as described earlier, the channel dose is smaller for a transistor which requires a lower threshold value (i.e., T1 less than T2 less than T3), and therefore, the impurity concentration is low at an interface between the oxide film and the bulk. A peak position of each profile is approximately the same as a position at which each channel dope layer is formed.
Now, a description will be given on a method of manufacturing the N-channel MOS transistors T1, T2 and T3 of the sense amplifier portion, the peripheral circuit portion and the memory cell array portion, with reference to FIGS. 69 to 74.
At a step shown in FIG. 69, the LOCOS layer (i.e., field oxide film) 2 is formed into a thickness of 4,000 xc3x85, for instance, by a LOCOS method on a surface of the semiconductor substrate 1 of-the P-type. Following this, boron ions, for instance, are implanted with the energy of 700 keV and at a dose of 1xc3x971013/cm2, thereby forming a P-type well region 101 within the semiconductor substrate 1. Although an N-type well region as well is formed in the semiconductor substrate 1 in order to form P-channel MOS transistors, this is not shown and a description will be omitted. Next, boron ions, for example, are implanted with the energy of 130 keV and at a dose of 5xc3x971012/cm2, thereby forming the channel cut layer 102 within the semiconductor substrate 1. The channel cut layer 102 is formed in such a shape which together with the LOCOS layer 2 creates the element-separated regions.
Next, at step shown in FIG. 70, at a predetermined position within the well region 101, the channel dope layer 103 is formed which has the lowest impurity concentration in accordance with the transistor T1 of the sense amplifier portion. At this stage, the channel dope layer 103 is formed also in regions within the transistors T2 and T3 of the peripheral circuis portion and the memory cell array portion. The channel dope layer 103 is formed by implanting boron ions, for instance, with the energy of 50 keV and at a dose of 1xc3x971012/cm2.
Next, at step shown in FIG. 71, a resist mask R201 is formed on the sense amplifier portion. An impurity is additionally implanted in a selective fashion into the channel dope layer 103 of the peripheral circuit portion and the memory cell array portion, thereby forming the channel dope layer 104 which has an impurity concentration in accordance with the transistor T2 of the peripheral circuit portion. At this stage, the channel dope layer 104 is formed also in a region within the transistor T3 of the memory cell array portion. The channel dope layer 104 is formed by implanting boron ions, for instance, with the energy of 50 keV and at a dose of 2xc3x971012/cm2.
Next, at step shown in FIG. 72, a resist mask R202 is formed on the sense amplifier portion and the peripheral circuit portion, an impurity is additionally implanted in a selective fashion into the channel dope layer 104 of the memory cell array portion, thereby forming the channel dope layer 105 which has an impurity concentration in accordance with the transistor T3 of the memory cell array portion. The channel dope layer 105 is formed by implanting boron ions, for instance, with the energy of 50 keV and at a dose of 2xc3x971012/cm2.
Next, at step shown in FIG. 73, after forming an oxide film 31 which will become the gate oxide film 3 on a main surface of the semiconductor substrate 1 by a thermal oxide method, a doped polysilicon layer 41, for instance, is formed as a gate electrode material on the oxide film 31 by a CVD method. The oxide film 31 has a thickness of about 100 xc3x85, whereas the doped polysilicon layer 41 has a thickness of about 2,000 xc3x85. Phosphorus (P) is used as an impurity. The concentration of the impurity is about 5xc3x971020/cm3.
Next, at step shown in FIG. 74, a resist mask R203 is formed on the doped polysilicon layer 41. By patterning, the gate electrode 4 and the gate oxide film 3 are formed.
Following this, after forming the LDD layers 107 in the sense amplifier portion, the peripheral circuit portion and the memory cell array portion by ion implantation, the side wall oxide film 5 is formed on a side surface of the gate oxide film 3 and the gate electrode 4 into a thickness of about 1,000 xc3x85. Using the side wall oxide film 5 as a mask, by ion implantation, the source/drain layers 106 are formed. In this manner, the structure of the DRAM shown in FIG. 67 is obtained.
Now, the LDD layers 107 are obtained by injecting arsenic (As) ions, for instance, with the energy of 30 keV and at a dose of 1xc3x971013/cm2. Meanwhile, the source/drain layers 106 are obtained by injecting arsenic ions, for instance, with the energy of 50 keV and at a dose of 1xc3x971015/cm2 and thereafter annealing at 850xc2x0 C. for 60 minutes.
Although this is followed by formation of a capacitor, an inter-layer insulation film, a wiring layer and the like to form the DRAM, this will not be described nor is shown in the drawings.
As described above, in the conventional DRAM, to form transistors which have different characteristics from each other and which are used in the sense amplifier portion, the peripheral circuit portion, the memory cell array portion and the like within one chip, the impurity concentration of the channel dope layer is changed in accordance with each transistor and the threshold value is adjusted.
However, the higher the impurity concentration of the channel dope layer is, the higher the threshold value becomes. At the same time, since the impurity concentration is high at a junction portion between a diffusion layer and the substrate, a leak current from the diffusion layer (i.e., diffusion layer leak) increases. In other words, the threshold value and the diffusion layer leak are in a trade-off relationship with each other, and therefore, a leak current is determined automatically once the threshold value is determined. Thus, the trade-off relationship between the two imposes a restriction on designing of the circuit.
As a second conventional example, a structure of a flash memory 700 in which a plurality of types of transistors are formed and a method of manufacturing the same will be described.
FIG. 75 shows a structure of the flash memory 700 (cell structure). In general, a flash memory is different from a DRAM in using a high voltage, such as 10V, for writing and erasing. To this end, in the flash memory 700 shown in FIG. 75, a charge pump circuit 710 is disposed as a step-up circuit.
The flash memory 700 comprises not only a memory cell array portion 701 for storing data, but also a high-voltage resistant portion, such as an X decoder 703 and a Y dencoder 704, which is used after stepping up, a peripheral circuit portion (i.e., an address buffer 702, a row/column clock portion 705, an I/O pass portion 706, a data register portion 707, a sense amplifier portion 708, an operation control portion 709), and the like. Although any these portions are formed by transistors, due to differences between voltages used, a plurality of types of transistors which have different characteristics from each other are needed.
For instance, a transistor in the memory cell array portion 701 demands an oxide film thickness of about 100 xc3x85, for example, in order to guarantee the reliability of a tunnel oxide film. However, a high amount of current is demanded in the peripheral circuit portion for the purpose of a high-speed operation, and therefore, an oxide film thickness is often set smaller than that of the memory cell array portion 701. Still, in the high-voltage resistant portion, a transistor which withstands a voltage of 10V necessary. Hence, it is necessary to use a thick oxide film which is as thick as 250 xc3x85, for instance. In short, a plurality of types of transistors which have different oxide film thicknesses from each other are needed within the flash memory which is in the form of one chip.
In the following, an example where an oxide film thickness is changed in accordance with a transistor will be described. FIG. 76 shows (in a partial view) an example of a structure of a flash memory which is fabricated by a conventional manufacturing method. Cross sections of N-channel MOS transistors T11 to T13 which are used for the high-voltage resistant portion, the peripheral circuit portion, and the memory cell array portion are shown.
In FIG. 76, the N-channel MOS transistors T11 to T13 are formed within a P-type well layer 121 which is formed on the same semiconductor substrate 21 (of the P-type). The well layer 121 is element-separated by a channel cut layer 122, which is formed within the well layer 121, and a LOCOS layer 22 in such a manner that the N-channel MOS transistors T11 to T13 are formed in regions which are created by element separation.
The N-channel MOS transistor T11 of the high-voltage resistant portion comprises a pair of source/drain layers 126 formed within the well layer 121 independently of each other but parallel to each other and a pair of LDD layers 127 formed adjacent to edge portions facing each other of the source/drain layers 126.
A gate oxide film 26 is formed on the LDD layers 127, and a gate electrode 29 is formed on the gate oxide film 26. A side wall oxide film 30 is formed on a side surface of the gate oxide film 26 and the gate electrode 29. Within the well layer 121 under the gate electrode 29, a channel dope layer 123 is formed.
The N-channel MOS transistor T12 of the peripheral circuit portion comprises a pair of source/drain layers 126 formed within the well layer 121 independently of each other but parallel to each other and a pair of LDD layers 127.
A gate oxide film 25 is formed on the LDD layers 127, and a gate electrode 29 is formed on the gate oxide film 25. A side wall oxide film 30 is formed on a side surface of the gate oxide film 25 and the gate electrode 29. Within the well layer 121 under the gate electrode 29, a channel dope layer 124 is formed.
The N-channel MOS transistor T13 of the memory cell array portion comprises a pair of source/drain layers 126 formed within the well layer 121 independently of each other but parallel to each other. A tunnel oxide film 23 is formed on edge portions of the source/drain layers 126. A floating gate electrode 27, an inter-layer insulation film 24 and a control gate electrode 28 are formed in this order on the tunnel oxide film 23.
The side wall oxide film 30 is formed on a side surface of the tunnel oxide film 23, the floating gate electrode 27, the inter-layer insulation film 24 and the control gate electrode 28.
Within the well layer 121 under the floating electrode 27, a channel dope layer 125 is formed. The memory cell array portion has a gate array structure in which adjacent gates share one source/drain layer 126. Such structures are arranged successively.
A characteristic of the flash memory which is shown in FIG. 76 is that the thickness of the gate oxide film 26 of the N-channel MOS transistor T11 of the high-voltage resistant portion is largest, followed by the thickness of the tunnel oxide film 23 of the N-channel MOS transistor T13 of the memory cell array portion and the thickness of the gate oxide film 25 of the N-channel MOS transistor T12 of the peripheral circuit portion in this order.
FIG. 77 shows the thicknesses of the respective gate oxide films. In FIG. 77, there are shown the N-channel MOS transistors of the high-voltage resistant portion, the peripheral circuit portion, and the memory cell array portion in this order along the horizontal axis from the left-hand side.
Table 2 shows figures regarding the structures of the N-channel MOS transistors T11 to T13.
In Table 2, the thicknesses of the gate oxide films of the N-channel MOS transistors T11, T12 and T13 are 250 xc3x85, 80 xc3x85 and 100 xc3x85, respectively.
Now, a description will be given on a method of manufacturing the N-channel MOS transistors T11, T12 and T13 of the high-voltage resistant portion, the peripheral circuit portion and the memory cell array portion, with reference to FIGS. 78 to 91.
First, at a step shown in FIG. 78, the LOCOS layer (i.e., field oxide film) 22 is formed into a thickness of 4,000 xc3x85, for instance, by a LOCOS method on a surface of the semiconductor substrate 21 of the P-type. Following this, boron ions, for instance, are implanted with the energy of 700 keV and at a dose of 1xc3x971013/cm2, thereby forming a P-type well region 121 within the semiconductor substrate 21. Although an N-type well region as well is formed in the semiconductor substrate 21 in order to form P-channel MOS transistors, this is not shown and a description will be omitted. Next, boron ions, for example, are implanted with the energy of 130 keV and at a dose of 5xc3x971012/cm2, thereby forming the channel cut layer 122 within the semiconductor substrate 21. The channel cut layer 122 is formed in such a shape which together with the LOCOS layer 22 creates the element-separated regions.
Next, a channel dope layer 120 is formed at predetermined positions of the high-voltage resistant portion, the peripheral circuit portion and the memory cell array portion within the well region 121. The channel dope layer 120 is formed by implanting boron ions, for instance, with the energy of 50 keV and at a dose of 5xc3x971012/cm2.
Next, at a step shown in FIG. 79, after forming an oxide film 231 which will become the tunnel oxide film 23 on a main surface of the semiconductor substrate 21 by a thermal oxide method, a doped polysilicon layer 271, for instance, is formed as a gate electrode material on the oxide film 231 by a CVD method. The oxide film 231 has a thickness of about 100 xc3x85, whereas the doped polysilicon layer 271 has a thickness of about 1,000 xc3x85. Phosphorus (P) is used as an impurity. The concentration of the impurity is about 1xc3x971020/cm3.
Next, at a step shown in FIG. 80, a resist mask R221 is formed selectively on the doped polysilicon layer 271 within the memory cell array portion. In this case, the resist mask R221 is formed along the gate-width direction of the memory cell array portion. A portion of the doped polysilicon layer 271 which is not covered with the resist mask R221 is removed by anisotropic etching. FIG. 81 shows this condition.
FIG. 81 is a plan view viewing FIG. 80 from the upper surface side (i.e., the side on which the resist mask R221 is formed). Within the memory cell array portion, the resist mask R221 is formed as rectangle islands which are arranged regularly. The resist mask R221 is formed to cover an active layer AL which has a configuration like a rectangle island and an LOCOS layer LL around the same. Within the high-voltage resistant portion and the peripheral circuit portion, since the resist mask R is not formed, the active layer AL is exposed.
Next, after removing the resist mask R221, at a step shown in FIG. 82, an insulation film 241, which will become the inter-layer insulation film 24 which insulates the floating gate from the control gate, is formed by a CVD method. This film has a structure in which a TEOS (tetraethyl orthosilicate) film, a nitride film (Si3N4) film, a TEOS film each having a thickness of 100 xc3x85 are stacked in this order. The inter-layer insulation film 24 is referred to as xe2x80x9cONO filmxe2x80x9d in some cases. The insulation film 241 is formed on the high-voltage resistant portion and the peripheral circuit portion as well.
Next, at a step shown in FIG. 83, a resist mask R222 is formed on the insulation film 241 of the memory cell array portion, and the insulation film 241 in all other regions is removed. In this case, in the other regions, the oxide film 231 is removed as well. FIG. 84 shows this condition.
FIG. 84 is a plan view viewing FIG. 83 from the upper surface side (i.e., the side on which the resist mask R222 is formed). The resist mask R222 is formed to entirely cover the memory cell array portion. However, within the high-voltage resistant portion and the peripheral circuit portion, since the resist mask R222 is not formed, the active layer AL is exposed.
Next, after removing the resist mask R222, at a step shown in FIG. 85, an oxide film 261 which will become the gate oxide film 26 is formed entirely on the main surface of the semiconductor substrate 21 by a thermal oxide method. At this stage, since the insulation film 241 on the memory cell array portion includes the nitride film, the insulation film 241 is not oxidized and the thickness of the insulation film 241 is maintained. The thickness of the oxide film 261 is about 170 xc3x85.
Next, at a step shown in FIG. 86, regions other than the peripheral circuit portion are covered with a resist mask R223 and the oxide film 261 on the oxide film 261 is removed by wet etching. FIG. 87 shows this condition.
FIG. 87 is a plan view viewing FIG. 86 from the upper surface side (i.e., the side on which the resist mask R223 is formed). The resist mask R223 is formed to entirely cover the memory cell array portion and the high-voltage resistant portion. However, within the peripheral circuit portion, since the resist mask R223 is not formed, the active layer AL is exposed.
Next, after removing the resist mask R223, at a step shown in FIG. 88, an oxide film 251 which will become the gate oxide film 25 is formed by a thermal oxide method. At this stage, since the insulation film 241 on the memory cell array portion includes the nitride film, the insulation film 241 is not oxidized and the thickness of the insulation film 241 is maintained. However, within the high-voltage resistant portion, the oxide film 261 grows and gains film thickness. The thickness of the oxide film 251 is about 80 xc3x85. The oxide film 261 grows into about 250 xc3x85.
Next, at a step shown in FIG. 89, a doped polysilicon layer 291 is formed, as a gate electrode material, entirely on the main surface of the semiconductor substrate 21 by a CVD method. The thickness of the doped polysilicon layer 291 is about 2,000 xc3x85. Phosphorus (P) is used as an impurity. The concentration of the impurity is about 5xc3x971020/cm3.
Next, at a step shown in FIG. 90, a resist mask ,7224 is formed on the doped polysilicon layer 291 and patterned. FIG. 91 shows this condition.
FIG. 91 is a plan view viewing FIG. 90 from the upper surface side (i.e., the side on which the resist mask R224 is formed). The resist mask R224 is formed to be perpendicular to the active layer AL which has a rectangular configuration.
As a result of patterning, the gate oxide film 26 and gate electrode 29 are formed within the high-voltage resistant portion, the gate oxide film 25 and gate electrode 29 are formed within the peripheral circuit portion, and the tunnel oxide film 23, the floating gate electrode 27 and the control gate electrode 28 are formed within the memory cell array portion.
Following this, after forming the LDD layers 127 by implanting ions into the high-voltage resistant portion and the peripheral circuit portion, the side wall oxide film 30 of about 1,000 xc3x85 in thickness is formed on a side surface of the gate oxide film 26 and gate electrode 29, on a side surface of the gate oxide film 25 and gate electrode 29, and on a side surface of the tunnel oxide film 23, the floating gate electrode 27, the inter-layer insulation film 24 and the control gate electrode 28. Using the side wall oxide film 30 as a mask, by ion implantation, the source/drain layers 126 are formed. In this manner, the structure of the flash memory which is shown in FIG. 76 is obtained.
Now, the LDD layers 127 are obtained by implanting arsenic ions, for instance, with the energy of 30 keV and at a dose of 1xc3x971013/cm2. Meanwhile, the source/drain layers 126 are obtained by injecting arsenic ions, for instance, with the energy of 50 keV and at a dose of 5xc3x971015/cm2 and thereafter annealing at 850xc2x0 C. for 60 minutes.
Although this is followed by formation of a capacitor, an inter-layer insulation film, a wiring layer and the like to form the flash memory, this will not be described nor is shown in the drawings.
As described above, as in the conventional DRAM, in the conventional flash memory, there is a trade-off relationship between a threshold value and a diffusion layer leak. The trade-off relationship imposes a restriction on designing of the circuit.
Further, since it is necessary to form a plurality of types of transistors which have different oxide film thicknesses from each other within the flash memory which is in the form of one chip, it is necessary to form the oxide films at more than one steps in some cases. For example, within the high-voltage resistant portion, at the step of removing the resist mask R223 (See FIG. 86), the oxide film 261 is grown further during formation of the oxide film 251 (See FIG. 88). That is, the oxide film 261 is formed at two steps. This leads to a higher possibility of allowing entry of an impurity or the like, which in turn degrades the reliability of the gate oxide film 26 or worsens the controllability of the film thickness. This further leads to a problem that the reliability of the N-channel MOS transistor T11 of the high-voltage resistant portion is lost, etc.
As a third conventional example, a structure of a DRAM 800 which comprises a logic circuit (hereinafter xe2x80x9cLOGIC in DRAMxe2x80x9d) and a method of manufacturing the same will be described.
The LOGIC in DRAM 800 is a device which executes a high performance and requires only a low cost, since a logic circuit is formed within the same chip so that the DRAM and the logic circuit, which have been heretofore formed as separate chips, are combined with each other.
As shown in FIG. 92, the LOGIC in DRAM 800 is roughly divided into a logic portion and a DRAM portion. A requirement to the logic portion is an operation at a high speed, that is, a high driving capability and a low capacity. Meanwhile, as described earlier, the DRAM portion includes a memory cell array portion in which a low leak current is demanded, a sense amplifier portion in which an operation at a low voltage is demanded, etc. That is, a plurality of types of transistors which have different characteristics from each other are needed within the LOGIC in DRAM 800 which is formed as one chip.
A conventional approach for forming transistors which have different characteristics from each other within one chip is to change an impurity profile of a channel dope layer or an oxide film thickness in accordance with a transistor. In the following, with respect to the DRAM portion, an example where an impurity concentration of a channel dope layer is changed in accordance with a transistor will be described, whereas with respect to the logic portion, an example where an oxide film thickness is changed in accordances with a transistor will be described.
FIG. 93 shows (in a partial view) an example of a structure of a LOGIC in DRAM which is fabricated by a conventional manufacturing method. Cross sections of N-channel MOS transistors T21 to T23 which are used for the logic portion and for the sense amplifier portion and the memory cell array portion of the DRAM portion are shown.
In FIG. 93, the N-channel MOS transistors T21 to T23 are formed within a P-type well layer 151 which is formed on the same semiconductor substrate 51 (of the P-type). The well layer 151 is element-separated by a channel cut layer 152 which is formed within the well layer 151 and a LOCOS layer 52 in such a manner that the N-channel MOS transistors T21 to T23 are formed in regions which are created by element separation.
The N-channel MOS transistor T21 of the logic portion comprises a pair of source/drain layers 156 formed within the well layer 151 independently of each other but parallel to each other and a pair of LDD layers 157 formed adjacent to edge portions facing each other of the source/drain layers 156.
A gate oxide film 54 is formed on the LDD layers 157, and a gate electrode 55 is formed on the gate oxide film 54. A side wall oxide film 56 is formed on a side surface of the gate oxide film 54 and the gate electrode 55. Within the well layer 151 under the gate electrode 55, a channel dope layer 155 is formed.
The N-channel MOS transistor T22 of the sense amplifier portion comprises a pair of source/drain layers 156 formed within the well layer 151 independently of each other but parallel to each other and a pair of LDD layers 157.
A gate oxide film 53 is formed on the LDD layers 157, and a gate electrode 55 is formed on the gate oxide film 53. The side wall oxide film 56 is formed on a side surface of the gate oxide film 53 and the gate electrode 55. Within the well layer 151 under the gate electrode 55, a channel dope layer 154 is formed.
The N-channels MOS transistor T13 of the memory cell array portion comprises a pair of source/drain layers 156 formed within the well layer 151 independently of each other but parallel to each other and a pair of LDD layers 157.
The gate oxide film 53 is formed on the source/drain layers 156 and the LDD layers 157, and the gate electrode 55 is formed on the gate oxide film 53. The side wall oxide film 56 is formed on a side surface of the gate oxide film 53 and the gate electrode 55. Within the well layer 151 under the gate electrode 55, a channel dope layer 153 is formed. The memory cell array portion has a gate array structure in which adjacent gates share one source/drain layer 156. Such structures are arranged successively. Table 3 shows figures regarding the structures of the N-channel MOS transistors T21 to T23.
In Table 3, impurity dose for forming the channel dope layers of the N-channel MOS transistors T21, T22 and T23 are 1xc3x971013/cm2, 1xc3x971012/cm2 and 5xc3x971012/cm2, respectively. Boron (B) is implanted as an impurity for either layers with the implantation energy of 50 keV.
Further, the thicknesses of the gate oxide films of the N-channel MOS transistors T21, T22 and T23 are 60 xc3x85, 100 xc3x85 and 100 xc3x85, respectively.
FIG. 94 shows impurity profiles of the N-channel MOS transistors T21, T22 and T23 of the logic portion, the sense amplifier portion and the memory cell array portion, all of which shown in FIG. 93, taken at cross sectional portions along A-Axe2x80x2 line, B-Bxe2x80x2 line and C-Cxe2x80x2 line, respectively.
In FIG. 94, a position (i.e., depth) in a cross sectional direction is shown along a horizontal axis and an impurity concentration is shown along a vertical axis. There are the gate electrode (polysilicon layer), the gate oxide film (SiO2 layer) and the well layer (bulk silicon layer) in this order along the horizontal axis from the left-hand side.
As shown in Table 3, the impurity concentration in the gate electrode stays uniformly at the same quantity among any transistors, and therefore, the A-Axe2x80x2 line, the B-Bxe2x80x2 line and the C-Cxe2x80x2 line are one atop the other and shown as overlapping straight lines (shown as two lines in the drawing to distinguish the A-Axe2x80x2 line). On the other hand, in the well layer, the channel dose is smaller for a transistor of the sense amplifier portion which requires a low threshold value, and therefore, the impurity concentration is low at an interface between the oxide film and the bulk. A peak position of each profile is approximately the same as a position at which each channel dope layer is formed.
FIG. 95 shows thicknesses of the respective gate oxide films. In FIG. 95, the N-channel MOS transistors of the logic portion, the sense amplifier portion and the memory cell array portion are shown in this order along the horizontal axis from the left-hand side. As shown in FIG. 95, in order to improve the current driving capability, the logic portion has a thinner oxide film thickness than those of the sense amplifier portion and the memory cell array portion of the DRAM portion.
In the following, a description will be given on a method of manufacturing the N-channel MOS transistors T21, T22 and T23 of the logic portion, the sense amplifier portion and the memory cell array portion of the DRAM portion, with reference to FIGS. 96 to 104.
First, at a step shown in FIG. 96, the LOCOS layer (i.e., field oxide film) 52 is formed into a thickness of 4,000 xc3x85, for instance, by a LOCOS method, on a surface of the semiconductor substrate 51 of the P-type. Following this, boron ions, for instance, are implanted with the energy of 700 keV and at a dose of 1xc3x971013/cm2, thereby forming a P-type well region 151 within the semiconductor substrate 51. Although an N-type well region as well is formed in the semiconductor substrate 51 in order to form P-channel MOS transistors, this is not shown and a description will be omitted. Next, boron ions, for example, are implanted with the energy of 130 keV and at a dose of 5xc3x971012/cm2, thereby forming the channel cut layer 152 within the semiconductor substrate 51. The channel cut layer 152 is formed in such a shape which together with the LOCOS layer 52 creates the element-separated regions.
Next, at step shown in FIG. 97, at a predetermined position within the well region 151, the channel dope layer 154 is formed which has the lowest impurity concentration in accordance with the transistor T22 of the sense amplifier portion. At this stage, the channel dope layer 154 is formed also in regions within the transistors T21 and T23 of the logic portion and the memory cell array portion. The channel dope layer 154 is formed by implanting boron ions, for instance, with the energy of 50 keV and at a dose of 1xc3x971012/cm2.
Next, at step shown in FIG. 98, a resist mask R251 is formed on the sense amplifier portion. An impurity is additionally implanted in a selective fashion into the channel dope layer 154 of the logic portion and the memory cell array portion, thereby forming the channel dope layer 153 which has an impurity concentration in accordance with the transistor T23 of the memory cell array portion. At this stage, the channel dope layer 153 is formed also in a region within the transistor T21 of the logic portion. The channel dope layer 153 is formed by implanting boron ions, for instance, with the energy of 50 keV and at a dose of 4xc3x971012/cm2.
Next, at step shown in FIG. 99, a resist mask R252 is formed on the sense amplifier portion and the memory cell array portion. An impurity is additionally implanted in a selective fashion into the channel dope layer 153 of the logic portion, thereby forming the channel dope layer 155 which has an impurity concentration in accordance with the transistor T21 of the logic portion. The channel dope layer 155 is formed by implanting boron ions, for instance, with the energy of 50 keV and at a dose of 5xc3x971012/cm2.
Next, at step shown in FIG. 100, an oxide film 531 which will become the gate oxide film 53 is formed on the main surface of the semiconductor substrate 51 by a thermal oxide method. The thickness of the oxide film 531 is about 40 xc3x85.
Next, at step shown in FIG. 101, the thickness of the oxide film 531 of the sense amplifier portion and the memory cell array portion is covered with a resist mask R253, and the thickness of the oxide film 531 which is located on the logic portion alone is selectively removed.
Next, after removing the resist mask R253, at a step shown in FIG. 102, an oxide film 541 which will become the gate oxide film 54 is formed on the main surface of the semiconductor substrate 51 by a thermal oxide method. At this stage, since the insulation film 531 on the sense amplifier portion and the memory cell array portion grows and gains film thickness. The thickness of the oxide film 541 is about 60 xc3x85. The oxide film 531 grows into about 100 xc3x85.
Next, at a step shown in FIG. 103, a doped polysilicon layer 551 is formed, as a gate electrode material, on the oxide film 531 and the oxide film 541 by a CVD method. The thickness of the doped polysilicon layer 551 is about 2,000 xc3x85. Phosphorus (P) is used as an impurity. The concentration of the impurity is about 1xc3x971020/cm3.
Next, at a step shown in FIG. 104, a resist mask R254 is formed on the doped polysilicon layer 551 and patterned. By patterning, the gate electrode 54 and the gate electrode 55 are formed in the logic portion while the gate oxide film 53 and the gate electrode 55 are formed in the sense amplifier portion and the memory cell array portion.
Following this, after forming she LDD layers 157 by implanting ions into the logic portion, the sense amplifier portion and the memory cell array portion, the side wall oxide film 56 of about 1,000 xc3x85 in thickness is formed on a side surface of the gate oxide film 54 and gate electrode 55 within the logic portion, and on a side surface of the gate oxide film 53 and gate electrode 55 within the sense amplifier portion and the memory cell array portion. Using the side wall oxide film 56 as a mask, by ion implantation, the source/drain layers 156 are formed. In this manner, the structure of the LOGIC in DRAM which is shown in FIG. 93 is obtained.
Now, the LDD layers 157 are obtained by implanting arsenic (As) ions, for instance, with the energy of 30 keV and at a dose of 1xc3x971013/cm2. Meanwhile, the source/drain layers 156 are obtained by injecting arsenic ions, for instance, with the energy of 50 keV and at a dose of 5xc3x97105/cm2 and thereafter annealing at 850xc2x0 C. for 30 minutes.
Although this is followed by formation of a capacitor, an inter-layer insulation film, a wiring layer and the like to form the LOGIC in DRAM, this will not be described nor is shown in the drawings.
As described above, in the conventional LOGIC in DRAM, to form transistors which are used in the logic portion, the sense amplifies portion and the memory cell array portion and which have different characteristics from each other within one chip, the impurity concentration of the channel dope layer is changed in accordance with each transistor and a threshold value is adjusted.
However, as the impurity concentration of the channel dope layer becomes higher, the threshold value increases. At the same time, a diffusion layer leak increases since the impurity concentration becomes high at a junction portion between a diffusion layer and the substrate, for instance. In other words, the threshold value and the diffusion layer leak are in a trade-off relationship with each other, and therefore, a leak current is determined automatically once the threshold value is determined. Thus, the trade-off relationship between the two imposes a restriction on designing of the circuit.
Further, in order to improve the current driving capability, the logic portion has a thinner oxide film thickness than those of the other portions. To this end, it is necessary to form a plurality of types of transistors which have different oxide film thicknesses from each other within the flash memory which is in the form of one chip, it is necessary to form the oxide films at more than one steps in some cases. For example, within the sense amplifier portion and the memory cell array portion, at the step of removing the resist mask R253 (See FIG. 101), the insulation film 531 is grown further during formation of the oxide film 541 (See FIG. 102). That is, the oxide film 531 is formed st two steps. This leads to a higher possibility of allowing entry of an impurity or the like, which in turn degrades the reliability of the gate oxide film 53 or worsens the controllability of the film thickness. This further leads to a problem that the reliability of the N-channel MOS transistors T22 and T23 of the sense amplifier portion and the memory cell array portion is lost, etc.
As a fourth conventional example, a structure of a flash memory 900 which comprises a logic circuit (hereinafter xe2x80x9cLOGIC in FLASHxe2x80x9d) and a method of manufacturing the same will be described.
One of RandD targets which are attracting an attention as a transistor becomes denser is development of a one-chip microcomputer in which a microcomputer is fabricated within one chip, while another RandD target under a close attention is a larger capacity. An element in which a flash memory and a MPU (micropsocessing unit) are formed within one chip, in particular, is called flash-consolidated logic as the one which is made public in 1995 IDEM SHORT COURSE PROGRAM, xe2x80x9cEMBEDDED FLASH MEMORY APPLICATIONS, TECHNOLOGY AND DESIGN,xe2x80x9d CLINTON KUO, MOTOROLA, and others.
FIG. 105 shows one example. As shown in FIG. 105, the LOGIC in FLASH 900 is roughly divided into a logic portion and a flash memory portion. A requirement to the logic portion is -an operation at a high speed, that is, a high driving capability and a low capacity.
The flash memory portion comprises a high-voltage resistant portion in which a high voltage is applied, a memory cell array portion in which a tunnel oxide film needs to be highly reliable, and the like. That is, a plurality of types of transistors which have different characteristics from each other are needed within the LOGIC in FLASH which is formed as one chip.
A conventional approach for forming transistors which have different characteristics from each other within one chip is to change an oxide film thickness in accordance with a transistor, or if necessary, to change an impurity profile of a at channel dope layer. In the following, an example where an oxide film thickness in accordance with a transistor while changing an impurity concentration of a channel dope layer will be described.
FIG. 106 shows (in a partial view) an example of a structure of a LOGIC in FLASH which is fabricated by a conventional manufacturing method. Cross sections of N-channel MOS transistors T31 to T33 which are used for the logic portion and for the high-voltage resistant portion and the memory cell array portion of the flash memory portion are shown.
In FIG. 106, the N-channel MOS transistors T31 to T33 are formed within a P-type well layer 171 which is formed on the same semiconductor substrate 71 (of the P-type). The well layer 171 is element-separated by a channel cut layer 171 which is formed within the well layer 171 and a LOCOS layer 72 in such a manner that the N-channel MOS transistors T31 to T33 are formed in regions which are created by element separation.
The N-channel MOS transistor T31 of the logic portion comprises a pair of source/drain layers 176 formed within the well layer 171 independently of each other but parallel to each other and a pair of LDD layers 177 formed adjacent to edge portions facing each other of the source/drain layers 176.
A gate oxide film 76 is formed on the LDD layers 177, and a gate electrode 79 is formed on the gate oxide film 76. A side wall oxide film 80 is formed on a side surface of the gate oxide film 76 and the gate electrode 79. Within the well layer 171 under the gate electrode 79, a channel dope layer 175 is formed.
The N-channel MOS transistor T32 of the high-voltage resistant portion of the flash memory portion comprises a pair of source/drain layers 176 formed within the well layer 171 independently of each other but parallel to each other and a pair of LDD layers 177.
A gate oxide film 75 is formed on the LDD layers 177, and a gate electrode 79 is formed on the gate oxide film 75. The side wall oxide film 80 is formed on a side surface of the gate oxide film 75 and the gate electrode 79. Within the well layer 171 under the gate electrode 79, a channel dope layer 173 is formed.
The N-channel MOS transistor T33 of the memory cell array portion of the flash memory portion comprises a pair of source/drain layers 176 formed within the well layer 171 independently of each other but parallel to each other. A tunnel oxide film 73 is formed on edge portions of the source/drain layers 176. A floating gate electrode 77, an inter-layer insulation film 74 and a control gate electrode 78 are formed in this order on the tunnel oxide film 73.
The side wall oxide film 80 is formed on a side surface of the tunnel oxide film 73, the floating gate electrode 77, the inter-layer insulation film 74 and the control gate electrode 78.
Within the well layer 171 under-the floating electrode 77, a channel dope layer 175 is formed. The memory cell array portion has a gate array structure in which adjacent gates share one source/drain layer 176. Such structures are arranged successively.
A characteristic of the flash memory which is shown in FIG. 106 is that the thickness of the gate oxide film 75 of the N-channel MOS transistor T32 of the high-voltage resistant portion is largest, followed by the thickness of the tunnel oxide film 73 of the N-channel MOS transistor T33 of the memory cell array portion and the thickness of the gate oxide film 76 of the N-channel MOS transistor T31 of the logic portion in this order, and that the impurity concentration of the channel dope layer 173 of the N-channel MOS transistor T32 of the high-voltage resistant portion is lower than those of the other chancels dope layers.
Table 4 shows figures regarding the structures of the N-channel MOS transistors T31 to T33.
In Table 4, the thicknesses of the gate oxide films of the N-channel MOS transistors T31, T32 and T33 are 60 xc3x85, 250 xc3x85 and 100 xc3x85, respectively.
Further, an impurity dose for forming the channel dope layer 173 of the N-channel MOS transistor T32 is 1xc3x971012/cm2, while an impurity dose for forming the channel dope layer 173 of the N-channel MOS transistors T31 and T33 is 1xc3x971013/cm2. Boron (B) is implanted as an impurity for either layers with the implantation energy of 50 keV.
FIG. 107 shows impurity profiles of the N-channel MOS transistors T31, T32 and T33 forming the sense amplifier portion, the peripheral circuit portion and the memory cell array portion, all of which shown in FIG. 106, taken at cross sectional portions along A-Axe2x80x2 line, B-Bxe2x80x2 line and C-Cxe2x80x2 line, respectively.
In FIG. 107, a position (i.e., depth) in a cross sectional direction is shown along a horizontal axis and an impurity concentration is shown along a vertical axis. There are the gate electrode (polysilicon layer), the gate oxide film (SiO2 layer) and the well layer (bulk silicon layer) in this order along the horizontal axis from the left-hand side.
As shown in Table 4, the impurity concentration in the gate electrode stays uniformly at the same quantity among any transistors, and therefore, the A-Axe2x80x2 line, the B-Bxe2x80x2 line and the C-Cxe2x80x2 line are one atop the other and shown as overlapping straight lines (shown as three lines in the drawing to distinguish the respective lines). On the other hand, in the well layer, the channel dose is smaller for a transistor of the high-voltage resistant portion which requires a low threshold value, and therefore, the impurity concentration is low at an interface between the oxide film and the bulk. A peak position of each profile is approximately the same as a position at which each channel dope layer is formed.
FIG. 108 shows thicknesses of the respective gate oxide films. In FIG. 108, the N-channel MOS transistors of the logic portion, the high-voltage resistant portion and the memory cell array portion are shown in this order along the horizontal axis from the left-hand side. As shown in FIG. 108, the oxide film of the high-voltage resistant portion of the flash memory portion is thickest, while the oxide film of the logic portion is the thinnest in order to improve the current driving capability,
In the following, a description will be given on a method of manufacturing the N-channel MOS transistors T31 to T33 of the logic portion, and of the high-voltage resistant portion and the memory cell array portion of the flash memory portion, which are shown in FIG. 106, with reference to FIGS. 109 to 122.
First, at a step shown in FIG. 109, the LOCOS layer (i.e., field oxide film) 72 is formed into a thickness of 4,000 xc3x85, for instance, by a LOCOS method, on a surface of the semiconductor substrate 71 of the P-type. Following this, boron ions, for instance, are implanted with the energy of 700 keV and at a dose of 1xc3x971013/cm2, thereby forming a P-type well region 171 within the semiconductor substrate 71. Although an N-type well region as well is formed in the semiconductor substrate 71 in order to form P-channel MOS transistors, this is not shown and a description will be omitted. Next, boron ions, for example, are implanted with the energy of 130 keV and at a dose of 5xc3x971012/cm2, thereby forming the channel cut layer 172 within the semiconductor substrate 71. The channel cut layer 172 is formed in such a shape which together with the LOCOS layer 72 creates the element-separated regions.
Next, the channel dope layer 173 which has the lowest impurity concentration is formed within the well region 171 of the transistors T32 of the high-voltage resistant portion. The channel dope layer 173 is formed by implanting boron ions, for instance, with the energy of 50 keV and at a dose of 1xc3x971012/cm2.
Next, an impurity is implanted-into the well region 171 of the transistors T31 and T33 of the logic portion and the memory cell array portion, thereby forming the channel dope layer 175 which has an impurity concentration in accordance with the transistors T31 and T33 of the logic portion and the memory cell array portion. The channel dope layer 175 is formed by implanting boron ions, for instance, with the energy of 50 keV and at a dose of 1xc3x971013/cm2.
Next, at a step shown in FIG. 110, after forming an oxide film 731 which will become the tunnel oxide film 73 on a main surface of the semiconductor substrate 71 by a thermal oxide method, a doped polysilicon layer 771, for instance, is formed as a gate electrode material on the oxide film 731 by a CVD method. The oxide film 731 has a thickness of about 100 xc3x85, whereas the doped polysilicon layer 771 has a thickness of about 1,000 xc3x85. Phosphorus (P) is used as an impurity. The concentration of the impurity is about 1xc3x971020/cm3.
Next, at a step shown in FIG. 111, a resist mask R261 is formed selectively on the doped polysilicon layer 771 within the memory cell array portion. In this case, the resist mask R261 is formed along the gate-width direction of the memory cell array portion. A portion of the doped polysilicon layer 771 which is not covered with the resist mask R261 is removed by anisotropic etching. FIG. 112 shows this condition.
FIG. 112 is a plan view viewing FIG. 111 from the upper surface side (i.e., the side on which the resist mask R261 is formed). Within the memory cell array portion, the resist mask R261 is formed as rectangle islands which are arranged regularly. The resist mask R261 is formed to cover an active layer AL which has a configuration like a rectangle island and an LOCOS layer LL around the same. Within the high-voltage resistant portion and the logic portion, since the resist mask R is not formed, the active layer AL is exposed.
Next, after removing the resist mask R261, at a step shown in FIG. 113, an insulation film 741, which will become the inter-layer insulation film 74 which insulates the floating gate from the control gate, is formed by a CVD method. This film has a structure in which a TEOS (tetraethyl orthosilicate) film, a nitride film (Si3N4) film, a TEOS film each having a thickness of 100 xc3x85 are stacked in this order. The inter-layer insulation film 74 is referred to as xe2x80x9cONO filmxe2x80x9d in some cases. The insulation film 741 is formed on the high-voltage resistant portion and the logic portion as well.
Next, at a step shown in FIG. 114, a resist mask R262 is formed on the insulation film 741 of the memory cell array portion, and the insulation film 741 in all other regions is removed. In this case, in the other regions, the oxide film 731 is removed as well. FIG. 115 shows this condition.
FIG. 115 is a plan view viewing FIG. 114 from the upper surface side (i.e., the side on which the resist mask R262 is formed). The resist mask R262 is formed to entirely cover the memory cell array portion. However, within the high-voltage resistant portion and the logic portion, since the resist mask R262 is not formed, the active layer AL is exposed.
Next, after removing the resist mask R262, at a step shown in FIG. 116, an oxide film 751 which will become the gate oxide film 75 is formed entirely on the main surface of the semiconductor substrate 71 by a thermal oxide method. At this stage, since the insulation film 741 on the memory cell array portion includes the nitride film, the insulation film 741 is not oxidized and the thickness of the insulation film 741 is maintained. The thickness of the oxide film 261 is about 190 xc3x85.
Next, at a step shown in FIG. 117, regions other than the logic portion are covered with a resist mask R263 and t he oxide film 751 on the logic portion is removed by we t etching. FIG. 118 shows this condition.
FIG. 118 is a plan view viewing FIG. 117 from t he upper surface side (i.e., the side on which the resist mask R263 is formed). The resist mask R263 is formed to entirely cover the memory cell array portion and the high-voltage resistant portion. However, within the logic portion, since the resist mask R263 is not formed, the active layer AL is exposed.
Next, after removing the resist mask R263, at a step shown in FIG. 119, an oxide film 761 which will become the gate oxide film 76 is formed by a thermal oxide method. At this stage, since the insulation film 741 on the memory cell array portion includes the nitride film, the insulation film 741 i s not oxidized and the thickness of the insulation film 741 is maintained. However, within the high-voltage resistant portion, the oxide film 751 grows and gains film thickness. The thickness of the oxide film 761 is about 60 xc3x85. The oxide film 751 grows into about 250 xc3x85.
Next, at a step shown in FIG. 120, a doped polysilicon layer 791 is formed, as a gate electrode material, entirely on the main surface of the semiconductor substrate 71 by a CVD method. The thickness of the doped polysilicon layer 791 is about 2,000 xc3x85. Phosphorus (P) is used as an impurity. The concentration of the impurity is about 5xc3x971020/cm3.
Next, at a step shown in FIG. 121, a resist mask R264 is formed on the doped polysilicon layer 791 and patterned. FIG. 122 shows this condition.
FIG. 122 is a plan view viewing FIG. 121 from the upper surface side (i.e., the side on which the resist mask R264 is formed). The resist mask R264 is formed to be perpendicular to the active layer AL which has a rectangular configuration.
As a result of patterning, the gate oxide film 76 and gate electrode 79 are formed within the logic portion, the gate oxide film 76 and gate electrode 79 are formed within the high-voltage resistant portion, and the tunnel oxide film 73, the floating gate electrode 77 and the control gate electrode 78 are formed within the memory cell array portion.
Following this, after forming the LDD layers 177 by implanting ions into the logic portion and the high-voltage resistant portion, the side wall oxide film 80 of about 1,000 xc3x85 in thickness is formed on a side surface of the gate oxide film 76 and gate electrode 79, on a side surface of the gate oxide film 76 and gate electrode 79, and on a side surface of the tunnel oxide film 73, the floating gate electrode 77, the inter-layer insulation film 74 and the control gate electrode 78. Using the side wall oxide film 80 as a mask, by ion implantation, the source/drain layers 176 are formed. In this manner, the structure of the flash memory which is shown in FIG. 106 is obtained.
Now, the LDD layers 177 are obtained by implanting arsenic ions, for instance, with the energy of 30 keV and at a dose of 1xc3x971013/cm2. Meanwhile, the source/drain layers 176 are obtained by injecting arsenic ions, for instance, with the energy of 50 keV and at a dose of 5xc3x971015/cm2 and thereafter annealing at 850xc2x0 C. for 30 minutes.
Although this is followed by formation of a capacitor, an inter-layer insulation film, a wiring layer and the like to form the LOGIC in FLASH, this will not be described nor is shown in the drawings.
As described above, in the conventional LOGIC in FLASH, to form transistors which are used in the logic portion, the high-voltage resistant portion and the memory cell array portion and which have different characteristics from each other within one chip, the impurity concentration of the channel dope layer is changed in accordance with each transistor and a threshold value is adjusted.
However, as the impurity concentration of the channel dope layer becomes higher, the threshold value increases. At the same time, a diffusion layer leak increases since the impurity concentration becomes high at a junction portion between a diffusion layer and the substrate, for instance. In other words, the threshold value and the diffusion layer leak are in a trade-off relationship with each other, and therefore, a leak current is determined automatically once the threshold value is determined. Thus, the trade-off relationship between the two imposes a restriction on designing of the circuit.
Further, in the logic portion, in order to attain a high driving capability, it is necessary to form a thinner gate oxide film than those of the other portions. To this end, it is necessary to form a plurality of types of transistors which have different oxide film thicknesses from each other within the flash memory which is in the form of one chip, it is necessary to form the oxide films at more than one steps in some cases. For example, within the high-voltage resistant portion, at the step of removing the resist mask R263 (See FIG. 117), the insulation film 751 is grown further during formation of the oxide film 761 (See FIG. 118). That is, the oxide film 751 is formed at two steps. This leads to a higher possibility of allowing entry of an impurity or the like, which in turn degrades the reliability of the gate oxide film 75 or worsens the controllability of the film thickness. This further leads to a problem that the reliability of the N-channel MOS transistor T32 of the high-voltage resistant portion is lost, etc.
As described above, in a semiconductor device in which a plurality of types of transistors are formed within one chip, threshold values are heretofore adjusted by changing the impurity concentrations of the channel dope layers in accordance with the transistors. However, since there is a trade-off relationship between a threshold value and a diffusion layer leak, a leak current is determined automatically once the threshold value is determined. Thus, the trade-off relationship between the two imposes a restriction on designing of the circuit. In addition, it is necessary to form the gate oxide films at more than one steps. This leads to a higher possibility of allowing entry of an impurity or the like, which in turn degrades the reliability of the gate oxide films or worsens the controllability of the film thickness. This further leads to a problem that the reliability of the transistors is deteriorated.
A first aspect of the present invention is directed to a semiconductor device including at least one of a first to a third types of transistors on a semiconductor substrate, a transistor of the first type comprises: a first semiconductor layer of a first conductivity type which is formed in a surface of the semiconductor substrate; a first channel dope laser of the first conductivity type which is formed selectively in the first semiconductor layer; and a first control electrode which is formed at a position which faces the first channel dope layer, on the first semiconductor layer, a transistor of the second type comprises: a second semiconductor layer of the first conductivity type which is formed in the surface of the semiconductor substrate; a second channel dope layer of the first conductivity type which is formed selectively in the second semiconductor layer; and a second control electrode which is formed at a position which faces the second channel dope layer, on the second semiconductor layer, a transistor of the third type comprises: a third semiconductor layer of the first conductivity type which is formed in the surface of the semiconductor substrate; a third channel dope layer of the first conductivity type which is formed selectively in the third semiconductor layer; and a third control electrode which is formed at a position which faces the third channel dope layer, on the third semiconductor layer, and at least one of the first to the third control electrodes internally includes an impurity layer of the second conductivity type having a concentration distribution in the direction of depth.
According to the first aspect of the present invention, since at least one of the first to the third control electrodes internally includes an impurity layer of the second conductivity type having a concentration distribution in the direction of depth, it is possible to change the impurity concentrations of the control electrodes independently of each other among the first to the third types of transistors which have different characteristics from each other (e.g., having different required specifications from each other), and hence, it is possible to change the effective thicknesses of the gate oxide films, so that threshold values are set. Further, since it is possible to change the effective thicknesses of the gate oxide films by changing the impurity concentrations of the control electrodes, it is not necessary to form the gate oxide films of the transistors which have different breakdown voltages from each other to have different thicknesses from each other.
According to a second aspect of the invention, in the semiconductor device of the first aspect, the transistor of the first type comprises: a pair of first semiconductor regions of the second conductivity type formed selectively and independently of each other within the first semiconductor layer; and a first gate oxide film which is formed on the first semiconductor layer between the pair of first semiconductor regions, the first control electrode is formed on the first gate oxide film, the first channel dope layer is formed between the pair of first semiconductor regions within the first semiconductor layer, the transistor of the second type comprises: a pair of second semiconductor regions of the second conductivity type formed selectively and independently of each other within the second semiconductor layer; and a second gate oxide film which is formed on the second semiconductor layer between the pair of second semiconductor regions, the second control electrode is formed on the second gate oxide film, the second channel dope layer is formed between the pair of second semiconductor regions within the second semiconductor layer, the transistor of the third type comprises: a pair of third semiconductor regions of the second conductivity type formed selectively and independently of each other within the third semiconductor layer; and a third gate oxide film which is formed on the third semiconductor layer between the pair of third semiconductor regions, the third control electrode is formed on the third gate oxide film, the third channel dope layer is formed between the pair of third semiconductor regions within the third semiconductor layer, the first, the second and the third control electrodes include a first, a second and a third impurity layers, respectively, which have different impurity concentrations from each other, the first to the third gate oxide films have the same thickness, and the first to the third channel dope layers have the same impurity concentration.
Accordingly, in the second aspect of the invention, since the first to the third control electrodes includes the first to the third impurity layers which have different impurity concentrations from each other, the first to the third gate oxide films have the same thickness and the first to the third channel dope layers have the same impurity concentration, in a DRAM, for instance, by applying the first type of transistor as a sense amplifier circuit, the second type of transistor as a peripheral circuit and the third type of transistor as a memory cell array, the impurity concentrations of the control electrodes are each changed and the effective thicknesses of the gate oxide films are changed, so that it is possible to set threshold values. Hence, it is not necessary to change the impurity concentrations of the channel dope layers depending on the characteristics of the transistors unlike in the conventional techniques, and it is possible to fix the concentrations at such values with which a leak current (i.e., diffusion layer leak) from a diffusion layer can be suppressed as small as possible. Hence, by setting the impurity concentrations of the channel dope layers at such values with which a diffusion layer leak is as small as possible while setting threshold values by means of the impurity concentrations of the gate electrodes, it is possible to break the trade-off relationship between the threshold values and the diffusion layer leak and hence to eliminate a restriction imposed on circuit designing. To change the impurity concentrations of the gate electrodes independently is less influential over tse other structures than to change the impurity concentrations of the channel dope layers which are formed within the semiconductor substrate. That is, when ions are to be implanted into the semiconductor substrate, in particular, when implantation at a high dose is to be executed, this causes crystal deterioration of the semiconductor substrate. However, in the present invention, since ions are implanted into the gate electrodes which are located in the outer-most layer, this problem does not occur.
According to a third aspect of the invention, in the semiconductor device of the first aspect, the transistor of the first type comprises: a pair of first semiconductor regions of the second conductivity type formed selectively and independently of each other within the first semiconductor layer; and a first gate oxide film which is formed on the first semiconductor layer between the pair of first semiconductor regions, the first control electrode is formed on the first gate oxide film, the first channel dope layer is formed between the pair of first semiconductor regions within the first semiconductor layer, the transistor of the second type comprises: a pair of second semiconductor regions of the second conductivity type formed selectively and independently of each other within the second semiconductor layer; and a second gate oxide film which is formed on the second semiconductor layer between the pair of second semiconductor regions, the second control electrode is formed on the second gate oxide film, the second channel dope layer is formed between the pair of second semiconductor regions within the second semiconductor layer, the transistor of the third type comprises: a pair of third semiconductor regions of the second conductivity type formed selectively and independently of each other within the third semiconductor layer; a third gate oxide film which is formed on the third semiconductor layer between the pair of third semiconductor regions; a floating gate electrode which is formed on the third gate oxide film; and an inter-layer insulation film which is formed on the floating gate electrode, the third control electrode is formed on the inter-layer insulation film, the third channel dope layer is formed between the pair of third semiconductor regions within the third semiconductor layer, the first, the second and the third control electrodes include a first, a second and a third impurity layers, respectively, which have different impurity concentrations from each other, the first and the second gate oxide films have the same thickness which is a first thickness but the third gate oxide film has a second thickness which is thicker than the first thickness, and the first to the third channel dope layers have the same impurity concentration.
Accordingly, in the third aspect-of the invention, since the first and the second gate oxide films have the same first thickness but the third gate oxide film has a second thickness which is thinner than the first thickness while the first to the third channel dope layers have the same impurity concentration, in a flash memory, for instance, by applying the first type of transistor as a high-voltage resistant circuit, the second type of transistor as a peripheral circuit and the third type of transistor as a memory cell array, the impurity concentrations of the control electrodes are each changed and the effective thicknesses of the gate oxide films are changed. Hence, it is not necessary to change the thicknesses of the gate oxide films of the transistors which have different breakdown voltages from each other to have different thicknesses from each other. Further, it is possible to set threshold values by changing the effective thicknesses of the gate oxide films, it is not necessary to change the impurity concentrations of the channel dope layers depending on tse characteristics of the transistors, and it is possible to fix the concentrations at such values with which a leak current (i.e., diffusion layer leak) from a diffusion layer can be suppressed as small as possible. Hence, by setting the impurity concentrations of the channel dope layers at such values with which a diffusion layer leak is as small as possible while adjusting the breakdown voltage characteristics and the threshold values by means of the impurity concentrations of the gate electrodes, it is possible to satisfy the requirements regarding the breakdown voltages, to break the trade-off relationship between the threshold values and the diffusion layer leak, and hence, to eliminate a restriction imposed on circuit designing. Still further, in the case of forming gate oxide films having different thicknesses from each other as well, by changing the effective thicknesses of the gate oxide films, it is possible to reduce the types of the gate oxide films. This makes it possible to simplify the manufacturing steps of manufacturing the gate oxide films and to obtain gate oxide films which are excellent in reliability and controllability of controlling film thickness.
According to a fourth aspect of the invention, in the semiconductor device of the first aspect, the transistor of the first type comprises: a pair of first semiconductor regions of the second conductivity type formed selectively and independently of each other within the first semiconductor layer; and a first gate oxide film which is formed on the first semiconductor layer between the pair of first semiconductor regions, the first control electrode is formed on the first gate oxide film, the first channel dope layer is formed between the pair of first semiconductor regions within the first semiconductor layer, the transistor of the second type comprises: a pair of second semiconductor regions of the second conductivity type formed selectively and independently of each other within the second semiconductor layer; and a second gate oxide film which is formed on the second semiconductor layer between the pair of second semiconductor regions, the second control electrode is formed on the second gate oxide film, the second channel dope layer is formed between the pair of second semiconductor regions within the second semiconductor layer, the transistor of the third type comprises: a pair of third semiconductor regions of the second conductivity type formed selectively and independently of each other within the third semiconductor layer; and a third gate oxide film which is formed on the third semiconductor layer between the pair of third semiconductor regions, the third control electrode is formed on the third gate oxide film, the third channel dope layer is formed between the pair of third semiconductor regions within the third semiconductor layer, the first and the second control electrodes include a first and a second impurity layers, respectively, which have the same impurity concentration with each other, the third control electrode includes a third impurity layer whose concentration is lower than those of the first and the second impurity layers, the first to the third gate oxide films have the same thickness, and the first and the third channel dope layers have the same impurity concentration.
Accordingly, in the fourth aspect of the invention, impurity layers the first and the second control electrodes include the first and the second impurity layers, respectively, which have the same impurity concentrations with each other, the third control electrode includes the third impurity layer whose concentration is lower than those of the first and the second impurity layers, the first to the third gate oxide films have the same thickness. Hence, in a LOGIC in DRAM, for instance, by applying the first type of transistor as a logic circuit, the second type of transistor as a sense amplifier circuit and the third type of transistor as a memory cell array, in the memory cell array portion where the impurity concentration is low, a depletion layer is created in a large area within the gate electrode, so that the oxide film thickness becomes effectively thick and the threshold value is high. Thus, by setting the impurity concentrations of the first to the third channel dope layers at such values with which a diffusion layer leak is as small as possible while setting the threshold values by means of the impurity concentrations of the first to the third control electrodes, it is possible to break the trade-off relationship between the threshold values and the diffusion layer leak and hence to eliminate a restriction imposed on circuit designing.
According to a fifth aspect of the invention, in the semiconductor device of the first aspect, wherein the transistor of the first type comprises: a pair of first semiconductor regions of the second conductivity type formed selectively and independently of each other within the first semiconductor layer; and a first gate oxide film which is formed on the first semiconductor layer between the pair of first semiconductor regions, the first control electrode is formed on the first gate oxide film, the first channel dope layer is formed between the pair of first semiconductor regions within the first semiconductor layer, the transistor of the second type comprises: a pair of second semiconductor regions of the second conductivity type formed selectively and independently of each other within the second semiconductor layer; and a second gate oxide film which is formed on the second semiconductor layer between the pair of second semiconductor regions, the second control electrode is formed on the second gate oxide film, the second channel dope layer is formed between the pair of second semiconductor regions within the second semiconductor layer, the transistor of the third type comprises: a pair of third semiconductor regions of the second conductivity type formed selectively and independently of each other within the third semiconductor layer; a third gate oxide film which is formed on the third semiconductor layer between the pair of third semiconductor regions; a floating gate electrode which is formed on the third gate oxide film; and an inter-layer insulation film which is formed on the floating gate electrode, the third control electrode is formed on the inter-layer insulation film, the third channel dope layer is formed between the pair of third semiconductor regions within the third semiconductor layer, the first and the third control electrodes include a first and a third impurity layers, respectively, which have the same impurity concentrations with each other, the second control electrode includes a second impurity layers whose concentration is lower than those of the first and the third impurity layers, the first and the second gate oxide films have the same thickness which is a first thickness but the third gate oxide film has a second thickness which is thicker than the first thickness, and the first to the third channel dope layers have the same impurity concentration.
Accordingly, in the fifth aspect of the invention, the first and the second gate oxide films have the same first thickness, but the third gate oxide film has a second thickness which is thicker than the first thickness, and the first to the third channel dope layers have the same impurity concentration. Hence, in a LOGIC in FLASH, for instance, by applying the first type of transistor as a logic circuit, the second type of transistor as a circuit in which a high breakdown voltage is required and the third type of transistor as a memory cell array, in the circuit in which a high breakdown voltage where the impurity concentration is low, a depletion layer is created in a large area within the gate electrode, so that the oxide film thickness becomes effectively thick and the threshold value is high. Thus, by setting the impurity concentrations of the first to the third the channel dope layers at such values with which a diffusion layer leak is as small as possible while setting the threshold values by means of the impurity concentrations of the first to the third the control electrodes, it is possible to break the trade-off relationship between the threshold values and the diffusion layer leak and hence to eliminate a restriction imposed on circuit designing.
A sixth aspect of the present invention is directed to a method of manufacturing a semiconductor device in which there are at least one of a first to a third types of transistors on a semiconductor substrate, comprising the steps of: (a) forming a first to a third semiconductor layers of the first conductivity type at positions within a surface of the semiconductor substrate at which the first to the third types of transistors are formed; (b) selectively forming a first, a second and a third channel dope layers of the first conductivity type within the first, the second and the third semiconductor layers, respectively, by ion implantation; and (c) forming a first to a third control electrodes at positions facing the first to the third channel dope layers on the first to the third semiconductor layers, wherein the step (c) of forming the first to the third control electrodes includes a step of forming an impurity layer of the first conductivity type which has a concentration distribution in the direction of depth within at least one of the first to the third control electrodes.
Accordingly, the method of manufacturing a semiconductor device of the sixth aspect of the invention is appropriate for manufacturing the semiconductor device of the first aspect of the invention.
According to a seventh aspect of the invention, in the method of manufacturing a semiconductor device of the sixth aspect, the step (c) comprises the steps of: forming an oxide film on the first to the third semiconductor layers; forming a first conductive layer on the oxide film; implanting an impurity of the second conductivity type into the first conductive layer at a dose n1 to thereby form a second conductive layer which has a concentration distribution in the direction of depth within the first conductive layer; masking over the second conductive layer at a position at which the third type of transistor is formed and implanting an impurity of the second conductivity type into the not-masked second conductive layer at a dose n2 to thereby form a third conductive layer which has a concentration distribution in the direction of depth within the second conductive layer; masking over the third and the second conductive layers at positions at which the second and the third type of transistors are formed and implanting an impurity of the second conductivity type into the not-masked third conductive layer at a dose n3 to thereby form a fourth conductive layer which has a concentration distribution in the direction of depth within the third conductive layer; and selectively removing the second to the fourth conductive layers and the oxide film by patterning, to thereby form a first gate oxide film and a first control electrode on the first semiconductor layer, a second gate oxide film and a second control electrode on the second semiconductor layer, and a third gate oxide film and a third control electrode on the third semiconductor layer.
Accordingly, the method of manufacturing a semiconductor device of the seventh aspect of the invention is appropriate for manufacturing the semiconductor device of the second aspect of the invention.
According to an eighth aspect of the invention, in the method of manufacturing a semiconductor device of the sixth aspect, the step (c) comprises the steps of: forming an oxide film on the first to the third semiconductor layers; forming a first conductive layer on the oxide film; patterning the first conductive layer and the oxide film to thereby selectively remove the first conductive layer and the oxide film; selectively implanting an impurity of the second conductivity type into the first conductive layer at a dose n1 to thereby form a second conductive layer which has a concentration distribution in the direction of depth within the first conductive layer; masking over the second conductive layer at a position at which the third type of transistor is formed and implanting an impurity of the second conductivity type into the not-masked second conductive layer at a dose n2 to thereby form a third conductive layer which has a concentration distribution in the direction of depth within the second conductive layer; and masking over the third and the second conductive layers at positions at which the second and the third type of transistors are formed and implanting an impurity of the second conductivity type into the not-masked third conductive layer at a dose n3 to thereby form a fourth conductive layer which has a concentration distribution in the direction of depth within the third conductive layer.
Accordingly, the method of manufacturing a semiconductor device of the eighth aspect of the invention is appropriate for manufacturing the semiconductor device of the second aspect of the invention. In addition, since patterning is performed before forming the second to the fourth conductive layers into which the impurity is implanted, the patterning step is easy, and hence, the manufacturing steps are shortened.
According to a ninth aspect of the invention, in the method of manufacturing a semiconductor device of the sixth aspect, the step (c) comprises the steps of: forming a first oxide film having a first thickness on the first to the third semiconductor layers; selectively forming a first conductive layer which ununiformly has an impurity of the second conductivity type on the first oxide film on the third semiconductor layer; selectively forming an insulation film on the first conductive layer while removing the first oxide film at positions where the first and the second types of transistors are formed; forming a second oxide film having a second thickness which is thinner than the first thickness on the first and the second semiconductor layer; forming a second conductive layer on the second oxide film and the insulation film; implanting an impurity of the second conductivity type into the second conductive layer at a dose n1 to thereby form a third conductive layer which has a concentration distribution in the direction of depth within the second conductive layer; masking over the third conductive layer at a position at which the first type of transistor is formed and implanting an impurity of the second conductivity type into the not-masked third conductive layer at a dose n2 which remains to thereby form a fourth conductive layer which has a concentration distribution in the direction of depth within the third conductive layer; masking over the third and the fourth conductive layers at positions at which the first and the third type of transistors are formed and implanting an impurity of the second conductivity type into the not-masked fourth conductive layer at a dose n3 which remains to thereby form a fifth conductive layer which has a concentration distribution in the direction of depth within the fourth conductive layer; and selectively removing the third to the fifth conductive layers, the first and the second oxide films, and the insulation film by patterning, to thereby form a first gate oxide film and a first control electrode on the first semiconductor layer, a second gate oxide film and a second control electrode on the second semiconductor layer, and a third gate oxide film, a floating gate electrode, an inter-layer insulation film and a third control electrode on the third semiconductor layer.
According to a tenth aspect of the invention, in the method of manufacturing a semiconductor device of the sixth aspect, the step (b) includes a step of forming the first and the third channel dope layers so that the first and the third channel dope layers have the same impurity concentration, and the step (c) comprises the steps of: forming an oxide film having a first thickness on the first to the third semiconductor layers; forming a first conductive layer on the oxide film; implanting an impurity of the second conductivity type into the first conductive layer at a dose n1 to thereby form a second conductive layer which has a concentration distribution in the direction of depth within the second conductive layer; masking over the second conductive layer at a position at which the third type of transistor is formed and implanting an impurity of the second conductivity type into the not-masked second conductive layer at a dose n2 which remains to thereby form a third conductive layer which has a concentration distribution in the direction of depth within the second conductive layer; selectively removing the second and the third conductive layers and the insulation film by patterning, to thereby form a first gate oxide film and a first control electrode on the first semiconductor layer, a second gate oxide film and a second control electrode on the second semiconductor layer, and a third gate oxide film and a third control electrode on the third semiconductor layer.
According to an eleventh aspect of the invention, in the method of manufacturing a semiconductor device of the sixth aspect, the step (c) comprises the steps of: forming a first oxide film having a first thickness on the first to the third semiconductor layers; selectively forming a first conductive layer which ununiformly has an impurity of the second conductivity type on the first oxide film on the third semiconductor layer; selectively forming an insulation film on the first conductive layer while removing the first oxide film at positions where the first and the second types of transistors are formed; forming a second oxide film having a second thickness which is thinner than the first thickness on the first and the second semiconductor layer; forming a second conductive layer on the second oxide film and the insulation film; implanting an impurity of the second conductivity type into the second conductive layer at a dose n1 to thereby form a third oxide film which has a concentration distribution in the direction of depth within the second conductive layer; masking over the third conductive layer at a position at which the second type of transistor is formed and implanting an impurity of the second conductivity type into the not-masked third conductive layer at a dose n2 which remains to thereby form a fourth conductive layer which has a concentration distribution in the direction of depth within the third conductive layer; and selectively removing the first, the third and the fourth conductive layers, the first and the second oxide films, and the insulation film by patterning, to thereby form a first gate oxide film and a first control electrode on the first semiconductor layer, a second gate oxide film and a second control electrode on the second semiconductor layer, and a third gate oxide film, a floating gate electrode, an inter-layer insulation film and a third control electrode on the third semiconductor layer.
Accordingly, the methods of manufacturing a semiconductor device of the ninth to the eleventh aspects of the invention is appropriate for mansfacturing the semiconductor devices of the third to the fifth aspects of the invention.
A twelfth aspect of the invention is directed a method of manufacturing a semiconductor device in which there are a first and a second types of transistors formed on a single semiconductor substrate, comprising the. steps of: (a) selectively forming a field oxide film on a main surface of the semiconductor substrate to thereby define a first and a second regions in which the first and the second types of transistors are formed; (b) forming an oxide film on the first and the second regions and over the field oxide film; (c) forming a conductive layer, which becomes a control electrode, on the oxide film; and (d) introducing an impurity of the same conductivity type as that of a source/drain layer into the conductive layer on at least one of the first and the second regions.
Accordingly, in the methods of manufacturing a semiconductor device of the twelfth aspect of ths invention, the impurity of the same conductivity type as that of the source/drain layer is implanted into the conductive layer on at least one of the first and the second regions. Hence, it is possible to obtain a semiconductor device in which the effective thicknesses of the gate oxide films are changed and threshold values are set by changing the impurity concentrations of the control electrodes between the first and the second types of transistors. Even when different voltages are applied to the control electrodes of the first and the second S types of transistors, it is not necessary to change the thicknesses of the oxide films. This simplifies the manufacturing steps than where it is necessary to form the oxide films separately.
According to a thirteenth aspect of the invention, in the method of manufacturing a semiconductor device of the first aspect, the step (d) includes the steps of: selectively forming a resist on said conductive layer on at least the first region among the first and she second regions and implanting the impurity around the resist by ion implantation; and thermally diffusing the impurity which is implanted to thereby introduce the impurity into the conductive layer on at least the first region among the first and the second regions.
Accordingly, in the methods of manufacturing a semiconductor device of the thirteenth aspect of the invention, since the impurity is implanted directly by thermal diffusion into the conductive layer on at least the first region among the first and the second regions, it is possible to adjust the impurity concentration finer than where impurity ions are implanted directly.
According to a fourteenth aspect of the invention, in the method of manufacturing a semiconductor device of the first aspect, the step (d) includes the steps of: selectively forming a resist on a portion extending from an edge portion of the conductive layer on at least the first region among the first and the second regions to the field oxide film and implanting the impurity into the conductive layer which is not covered with the resist by ion implantation; and thermally diffusing the impurity which is implanted to thereby introduce the impurity into the conductive layer on at least the first region among the first and the second regions in such a manner that the impurity-has a high concentration at a central portion taken in a plane direction but has a lower concentration with a distance toward the edge portion.
Accordingly, in the methods of manufacturing a semiconductor device of the fourteenth aspect of the invention, since the impurity is implanted into the conductive layer on at least the first region in such a manner that the impurity has a high concentration at a central portion taken in a plane direction but has a lower concentration with a distance toward the edge portion, the range in which a depletion layer is formed becomes larger within the edge portion of the conductive layer, the effective thickness of the oside film, and the threshold value is partially increased. In the case where an SOI substrate is used as the semiconductor substrate, for instance, a problem of a decreased threshold value due to the structure of the edge portion is solved.
According to a fifteenth aspect of the invention, in the method of manufacturing a semiconductor device of the first aspect, the step (c) includes a step of (c-1) stacking a first conductive layer which uniformly contains the impurity and the second conductive layer which does not contain the impurity to thereby form the conductive layers, and the step (d) includes a step of diffusing the impurity naturally from the first conductive layer into the second conductive layer with respect to the first and the second conductive layers at least on the first region to thereby distribute the impurity.
Accordingly, in the methods of manufacturing a semiconductor device of the fifteenth aspect of the invention, since the impurity is diffused naturally from the fisst conductive layer into the second conductive layer among the first and the second conductive layers at least on the first region to thereby distribute the impurity, it is possible to adjust the impurity concentration finer than where impurity ions are implanted directly.
According to a sixteenth aspect of the invention, in the method of manufacturing a semiconductor device of the first aspect, the step (c-1) includes a step of forming a diffusion suppression film which suppresses a quantity of diffusion of the impurity between the first conductive layer and the second conductive layer.
Accordingly, in the methods of manufacturing a semiconductor device of the sixteenth aspect of the invention, since the diffusion suppression film which suppresses a quantity of diffusion of the impurity is formed between the first conductive layer and the second conductive layer, it is possible to suppress diffusion of the impurity and adjust the quantity of diffusion.
Accordingly, an object of the present invention is to provide for a semiconductor device in which there is no trade-off relationship between a threshold value and a diffusion layer leak and it is not necessary to form gate oxide films at more than one steps, and to provide for a method of manufacturing such a semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.